Title:
【発明の名称】障害を有するマイクロ命令を訂正するためのデータ処理装置
Document Type and Number:
Japanese Patent JP3118002
Kind Code:
B2
Abstract:
PCT No. PCT/EP95/03394 Sec. 371 Date Dec. 16, 1996 Sec. 102(e) Date Dec. 16, 1996 PCT Filed Aug. 29, 1995 PCT Pub. No. WO97/08618 PCT Pub. Date Mar. 6, 1997The present invention relates to a data processing apparatus which comprises a microprogrammable processor 1, a random access control store 4 and a read only control store 5 for storage of microinstructions. The random access control store includes a flag microinstruction (REPmark1) for indicating that another microinstruction (add W, 2, W1), stored in the read only control store 5, is faulty. The control stores are coupled to a multiplexer 8 and are adapted to output the microinstructions in parallel to the multiplexer 8 which is in turn coupled to the processor and which selectively provides output from either the random access control store or the read only control store to the processor 1. The apparatus also includes a decoder coupled to the random access control store for observing the microinstructions output therefrom. The decoder is further coupled to inhibiting logic in the processor and outputs a signal if the flag microinstruction is output from the random access control store. The signal causes the inhibiting logic in the processor to inhibit the processor from carrying out the faulty microinstruction.
Inventors:
Getzlav, Claus, George
Plüger, Thomas
Coster, Ralph
Meltain, Cristian
Tast, Hans Werner
Plüger, Thomas
Coster, Ralph
Meltain, Cristian
Tast, Hans Werner
Application Number:
JP50973497A
Publication Date:
December 18, 2000
Filing Date:
August 29, 1995
Export Citation:
Assignee:
International Business Machines Corporation
International Classes:
G06F9/22; G06F8/65; G06F9/26; G06F9/30; G06F9/318; G06F9/32; G06F9/445; (IPC1-7): G06F9/22; G06F9/22
Domestic Patent References:
| JP60171537A | ||||
| JP532946A | ||||
| JP50116144A | ||||
| JP5843038A | ||||
| JP64109433A | ||||
| JP5466046A |
Attorney, Agent or Firm:
Jiro Yamamoto