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Patent Searching and Data


Title:
BOOSTER CIRCUIT
Document Type and Number:
Japanese Patent JP2001086735
Kind Code:
A
Abstract:

To suppress ripples by performing series/parallel switching of a first clamp capacitor with a positive signal delivered from a two-phase signal generating circuit and performing series/parallel switching of a second clamp capacitor with an inverted signal so that a smoothing capacitor can be charged at all times.

A booster circuit comprises a two-phase signal generating circuit comprising transistors Tr1, Tr2, Tr8, Tr9, Tr10, Tr11, first and second clamp capacitors C1, C2, a first clamp circuit comprising transistors Tr3, Tr4, Tr5, a second clamp circuit comprising transistors Tr12, Tr13, Tr14, first and second rectifier circuits comprising transistors Tr6, Tr7, and a smoothing capacitor C3. A positive signal, outputted from the two-phase signal generating circuit is used for series/parallel switching of the first clamp capacitor, and an inverted signal is used for series/parallel switching of the second clamp capacitor. Consequently, the capacitor C3 is charged at all times.


Inventors:
SUGURO AKIRA
Application Number:
JP25870199A
Publication Date:
March 30, 2001
Filing Date:
September 13, 1999
Export Citation:
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Assignee:
CITIZEN WATCH CO LTD
International Classes:
G02F1/133; H02M3/07; (IPC1-7): H02M3/07; G02F1/133