Title:
BOOSTING CIRCUIT FOR NONVOLATILE SEMICONDUCTOR MEMORY DEVICE
Document Type and Number:
Japanese Patent JP3726753
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To suppress rise in reference voltage accompanying rise in boosting voltage by releasing influence of parasitic capacitance at the time of turning on of a power source, at resetting, or the like.
SOLUTION: A rise period detecting circuit 350 detects a rise period from power source-on or power source-reset before boosting voltage HV reaches standby voltage (5.0 V), and outputs a detecting signal PWUP indicating the detected result. An oscillating circuit 340 generates a clock signal OSCK having a lower frequency Ha than a frequency Hr of a normal time while the detecting signal PWUP is at a high level (active) and outputting it. A charge pump circuit 310 boosts power source voltage Vdd based on the clock signal OSCK of a supplied frequency Ha, and boosts gently boosting voltage HV from power source voltage.
Inventors:
Natori complete recovery
Application Number:
JP2002014281A
Publication Date:
December 14, 2005
Filing Date:
January 23, 2002
Export Citation:
Assignee:
Seiko Epson Corporation
International Classes:
G11C16/06; G11C5/14; G11C8/08; G11C16/04; G11C16/30; H01L21/822; H01L27/04; H01L31/0328; H01L27/115; (IPC1-7): G11C16/06; G11C16/04
Domestic Patent References:
| JP1124198A | ||||
| JP10302492A |
Attorney, Agent or Firm:
Meisei International Patent Office
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