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Patent Searching and Data


Title:
BOOSTING CIRCUIT AND SEMICONDUCTOR DEVICE USING THE SAME
Document Type and Number:
Japanese Patent JP2000021179
Kind Code:
A
Abstract:

To more rapidly boost a voltage.

An NMOS capacitor 13 and a PMOS capacitor 18 for pumping up are connected in series with an output wiring 12. In a mid-point potential control circuit 20, a power source voltage VCC is connected to anode of a reverse-current preventive diode 22 and an node of a potential VM via a PMOS transistor 21, and a cathode of the diode 22 is connected to a ground line via a transistor 23. A control signal *BIN and a control signal AIN are respectively supplied to gates of the transistor 21 and the transistor 23. An end point potential control circuit 30 is connected between the gate of the transistor 23 and one end (VE) of the capacitor 18, and has inverters 31 and 32 connected in series. The signal *BIN is lowered at its level in response to a fall of an address transition detection signal AT.


Inventors:
NAKANO AKIHIRO
Application Number:
JP18789398A
Publication Date:
January 21, 2000
Filing Date:
July 02, 1998
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
G11C5/14; G11C8/08; G11C11/406; G11C11/407; G11C11/413; H02M3/07; (IPC1-7): G11C11/413; G11C11/407; H02M3/07
Attorney, Agent or Firm:
Matsumoto Shinkichi