Title:
BOOTSTRAP ADDRESS DECODER
Document Type and Number:
Japanese Patent JPH06243681
Kind Code:
A
Abstract:
PURPOSE: To supply a self-clocked signal which bootstraps a work line in a very short period.
CONSTITUTION: An address signal generated from address bits A1 and A2 and clock signals Y and Z are inputted to each clock generator 20. A bootstrap enable signal BEBAR outputted from a row address decoder 22 is inputted also to each clock generator 20. Signals 1 to 4 outputted from clock generators 20 are inputted to the row address decoder 22. An address signals generated from address bits A3 to A8 and a clock signal X are inputted also to the row address decoder 22. The row address decoder 22 selectively outputs work line signals WL0 to WL255.
Inventors:
KIMU SHII HAADEII
KENISU JIEI MOBUREI
KENISU JIEI MOBUREI
Application Number:
JP1939194A
Publication Date:
September 02, 1994
Filing Date:
February 16, 1994
Export Citation:
Assignee:
NIPPON STEEL SEMICONDUCTOR CO
UNITED MEMORIES INC
UNITED MEMORIES INC
International Classes:
G11C11/407; G11C8/10; (IPC1-7): G11C11/408
Attorney, Agent or Firm:
Masatake Shiga (2 outside)