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Title:
BREAK LEVEL DETECTING CIRCUIT
Document Type and Number:
Japanese Patent JPH01231545
Kind Code:
A
Abstract:

PURPOSE: To easily cope with the different break level detecting standards by synthesizing the input asynchronous data with the output of a pseudo stop pulse generating means to transmit them as the reception data and therefore reducing the scale of the break level detecting circuit.

CONSTITUTION: When all detection data D7∼D0 are equal to '0' and a framing error is detected, a pseudo stop pulse generating means 6 produces a pseudo stop pulse with a pseudo stop pulse generating instruction given from a control means 4. An asynchronous communication interface adaptor means 5 can detect the data following one character with addition of said pseudo stop pulse. In this case, a function is added to regard the detection of a break level when the pseudo stop pulse generating instructions are continuously sent to the means 4 up to (n). In such a way, the scale of a break level detecting circuit can be reduced and also it is possible to easily cope with the different break level detecting standards.


Inventors:
KOBAYASHI KATSUMI
Application Number:
JP5884888A
Publication Date:
September 14, 1989
Filing Date:
March 11, 1988
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L29/08; H04L13/00; (IPC1-7): H04L13/00
Attorney, Agent or Firm:
Sadaichi Igita



 
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