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Title:
BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPH0537332
Kind Code:
A
Abstract:

PURPOSE: To prevent a breakdown of a buffer by providing a circuit for detecting an error state that logic of an input side and an output side of the buffer is inconsistent, and controlling its buffer to a distble state.

CONSTITUTION: An output of an error detecting circuit 4 is inputted to an enable terminal 11 of a buffer 1, and when the output of the circuit 4 becomes an H level, the buffer 1 becomes a disable (invalid) state. The moment a power source is turned on, even if each part of the circuit is executing any operation, as the case may be, the output of the circuit 4 becomes an H level, the buffer 1 becomes a disable state, and in order to prevent it, a pull-up resistance 7 is provided. As a result, the circuit 4 outputs an L level. Accordingly, the buffer 1 becomes an enable state, and when an input of the buffer 1 is an H level, outputs of the buffers 1, 2 and 3 all output an H level, and thereafter, the level is varied in accordance with the input of the buffer 1.


Inventors:
TANDAI MARE
Application Number:
JP21437091A
Publication Date:
February 12, 1993
Filing Date:
July 31, 1991
Export Citation:
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Assignee:
NEC CORP
International Classes:
H01L21/8238; H01L27/092; H03K17/08; H03K19/003; H03K19/0175; (IPC1-7): H01L27/092; H03K17/08; H03K19/003; H03K19/0175
Attorney, Agent or Firm:
Yanagi Kawa Shin



 
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