PURPOSE: To make it possible to remove a noise by increasing an operation speed by using a cascaded delay circuit for the writing operation of a memory.
CONSTITUTION: As for a current switch as the delay circuit consisting of transistors Q2WQ4 and resistances R1 and R2, the value of potential VBB1 applied to the base of Q3 is so determined that Q2 and Q4 depending upon the value of signal inversion WE will be placed in the same state. Similarly, as for a current switch as the delay circuit composed of Q5WQ7 and resistance R3, the value of voltage VBB2 applied to the base of Q6 is so determined that Q5 and Q7 will be placed in the same state. Then, the output of the post-stage current switch and that of Q1 are wired-OR-ed by node B1 and its potential is applied as the output of buffer circuit B to memory cell array 20 by way of write driving circuit 10.
FUJIKI SUGURU
UCHIDA HIDEAKI
HIRATA MICHIYUKI
HITACHI OME ELECTRONIC CO
| JPS5235535A | 1977-03-18 |