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Patent Searching and Data


Title:
BUFFER CONTROL SYSTEM
Document Type and Number:
Japanese Patent JPS6412348
Kind Code:
A
Abstract:

PURPOSE: To simplify logic for the detection of a fault and the recovery of the fault, by checking the validity of the combination of a change bit and an exclusive bit in a directory provided in each processor which constitutes a multiprocessor.

CONSTITUTION: An AND gate 320 outputs a fault detecting signal 330 by deciding that the fault is generated in the exclusive bit E212 if the combination of the change bit C211 and the exclusive bit E212 is (10) in a case where an effective bit V210 is set at (1). Also, an OR gate 321 outputs the value of the exclusive bit E212 after the recovery of the exclusive bit E212 as a signal 311 by the change bit C211, the correctness of whose value is guaranteed. In other words, the OR of both bits becomes the exclusive bit E212 after the recovery of the fault in the case where the combination of the change bit C211 and the exclusive bit E212 is (10).


Inventors:
NAKAMURA KOJI
Application Number:
JP16710787A
Publication Date:
January 17, 1989
Filing Date:
July 06, 1987
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
G06F15/16; G06F11/08; G06F12/08; G06F15/177; G06F11/00; (IPC1-7): G06F12/08; G06F15/16
Attorney, Agent or Firm:
Kenjiro Take