BUFFER MANAGEMENT SYSTEM FOR COMMUNICATION CONTROLLER
Document Type and Number:
Japanese Patent JP3603956
PROBLEM TO BE SOLVED: To provide a buffer management system for a communication controller capable of accurately detecting a failure in a buffer management function of a communication control LSI and a buffer information transfer error.
SOLUTION: This buffer management system contains a host CPU 2 operating by program control, other devices 3 and 4, a communication controller 1 and a system bus 5 connecting respective devices and used to transfer information, and the communication controller 1 comprises an MPU 10, a main memory 12, a buffer memory 13, a DMAC 11, and communication control LSIs 14. The buffer is largely divided into three parts with respect to buffer allocation on the buffer memory 13 about buffer memory block allocation in an initial state, the next three-divided front block information is written as the next buffer chain information of a three-divided front block, the communication controller 1 is controlled in such a manner that the MPU 10 performs the next three- divided front block information according to a program stored in the main memory 12, and a failure in the buffer management function and a buffer information transfer error are detected by monitoring whether or not to effectively utilize the next three-divided front block information for the transfer of a frame to be transmitted/received on a communication line.
October 08, 2004
August 20, 2001
G06F13/00; H04L13/08; G06F13/00; H04L13/08; (IPC1-7): H04L13/08; G06F13/00