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Title:
BUFFERING SUBSTRATE FOE SEMICONDUCTOR ELEMENT
Document Type and Number:
Japanese Patent JP10064822
Kind Code:
A
Abstract:

To provide a technique for finer and even particle size of polycrystal silicon without increasing manufacture time and cost.

Used for a semiconductor device wherein a silicon layer 104 formed on a substrate 100 is irradiated with a laser beam 106 for crystallization so that a polycrystal silicon layer 108 is obtained, a buffer layer 102 is formed between the substrate 100 and the silicon layer 104. Relating to such buffering substrate as containing the buffer layer 102, the buffer layer 102 has a melting point higher than the limit temperature of the substrate 100, in addition, at crystallization of the silicon layer 104, it regulates nucleus generation density of the silicon layer 104 for forming an even silicon crystal particles on the buffer layer 102, and functions as a base for isotropic particle growth in crystallization process of the silicon layer 104.


Inventors:
Fork, David K.
Boyce, James B.
Mei, Ping
Ready, Steve
Johnson, Richard I.
Anderson, Greg B.
Application Number:
JP1997000148652
Publication Date:
March 06, 1998
Filing Date:
May 22, 1997
Export Citation:
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Assignee:
XEROX CORP
International Classes:
H01L21/02; H01L21/20; H01L21/205; H01L21/336; H01L27/12; H01L29/786; H01L21/02; H01L27/12; H01L29/66; (IPC1-7): H01L21/20; H01L21/02; H01L21/336; H01L27/12; H01L29/786