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Patent Searching and Data


Title:
BURN-IN METHOD OF MODULE ON WHICH MEMORY IC CHIP IS MOUNTED AND METHOD FOR MOUNTING THE MODULE ON MOTHER BOARD
Document Type and Number:
Japanese Patent JPH0823017
Kind Code:
A
Abstract:

PURPOSE: To conduct a selective burn-in at low cost wherein optionally determined burn-in conditions are applied to only memory IC chips and no influence is given to the other peripheral circuits.

CONSTITUTION: This method includes a process wherein first connection points 6a-6c, 7a-7c which are led out from a DRAM chip 3 and second connection points 4a-4c, 5a-5c which are electrically separated from the first connection points and which are led out from a CPU chip 2, a peripheral circuit, are installed on an MCM board 1 and a burn-in is conducted with the DRAM chip 3 and the CPU chip 2 being separated and a process wherein when this device is proved good by the result of the burn-in, the first and the second connection points are electrically connected.


Inventors:
MATSUZAKI AKIRA
Application Number:
JP15372194A
Publication Date:
January 23, 1996
Filing Date:
July 05, 1994
Export Citation:
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Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G01R31/28; H01L21/66; G01R31/26; (IPC1-7): H01L21/66; G01R31/26; G01R31/28
Attorney, Agent or Firm:
Mamoru Shimizu (1 person outside)