PURPOSE: To simplify a configuration and to reduce cost by providing an input and an output of each shift register to an error correction circuit and converting an output of the error correction circuit into a serial string and providing an output of it to use plural shift registers connected in series in place of a 2-port memory.

CONSTITUTION: N-sets of M-bit shift registers 101-10N are connected in series and burst data of M-bit × (N+1) block configuration are given to an input of the shift register 101 of the 1st stage. Simultaneously inputs and outputs of the shift registers 101-10N are given to an error correction circuit 11, and its output is converted into a serial string by a parallel/serial conversion circuit 12 and it is outputted. Since the plural shift registers 101-10N connected in series are used in place of a 2-port memory, the configuration is simplified and the cost is reduced. Furthermore, an output means 13 is provided to extract data before error correction, then analysis of data at evaluation or on the occurrence of a fault is attained.