BURST-TYPE RAM DEVICE AND ADDRESS GENERATING METHOD THEREOF

Japanese Patent JP3779500

B2

PROBLEM TO BE SOLVED: To provide a burst-type RAM device having a double-data speed method and consisting of improved address generating and decoding circuits, and address generating method thereof. SOLUTION: A burst-type RAM device has a memory cell array for storing data, and is provided with a double-data speed method wherein at least two data are input/output between one clock cycle. A first address generator 120, which receives initial addresses impressed externally and generates a series of addresses corresponding with a second half period of the clock cycle, and a second address generator 160, which receives the addresses from the first address generator 120 and generates a series of addresses corresponding with the second half period of the clock cycle by a burst information signal, are provided. In this structure, the addresses for the second half period of the clock cycle are automatically generated by a burst length and a mode, thereby an access speed of the burst-type access memory device having the double-data speed method can be improved.