Title:
BUS BRIDGE CIRCUIT
Document Type and Number:
Japanese Patent JP3206528
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a bus bridge circuit with which the efficiency of a system can be improved by decreasing the number of times for loading wait to a CPU in the case of reading data from various kinds of extension equipment on a general-purpose bus.
SOLUTION: When a write address coincidence signal (WM) is made active, an address cache controller 11 applies a latched read address to an address/data multiplexer 14. Further, the address cache controller 11 controls a bus controller 13 and starts burst read from the address applied to the address/data multiplexer 14, and data are fetched by a read FIFO 17. When the data required for a CPU 2 are already fetched into the read FIFO 17, without loading wait to the CPU, the address cache controller 1 transfers data to the CPU.
Inventors:
Moriharu Seki
Application Number:
JP33237497A
Publication Date:
September 10, 2001
Filing Date:
November 17, 1997
Export Citation:
Assignee:
NEC
International Classes:
G06F13/36; G06F12/08; (IPC1-7): G06F13/36; G06F12/08
Domestic Patent References:
| JP6168119A | ||||
| JP9231164A | ||||
| JP490038A |
Attorney, Agent or Firm:
Rock wall Fuyuki