Title:
BUS HANG DETECTION
Document Type and Number:
Japanese Patent JP2018116679
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To provide a monitoring method of an I2C bus status using a board management controller (BMC) and a hardware watch dog (HW) circuit.SOLUTION: The monitoring method includes a step of detecting invalidation of an I2C bus using an HW circuit, and determining whether or not the HW circuit can automatically reset a plurality of I2C devices on the I2C bus. The method includes: a step of resetting the plurality of I2C devices using the HW circuit when determining whether or not the HW circuit can automatically reset the I2C devices on the I2C bus; and a step of reporting the detected invalidation to BMC using the HW circuit when determining whether or not the HW circuit cannot automatically reset the plurality of I2C devices on the I2C bus. The method includes a step of processing the invalidation detected using the BMC.SELECTED DRAWING: Figure 2
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Inventors:
HUANG CHIH-CHIA
HSIAO MING-CHIH
HSIAO MING-CHIH
Application Number:
JP2017177846A
Publication Date:
July 26, 2018
Filing Date:
September 15, 2017
Export Citation:
Assignee:
QUANTA COMP INC
International Classes:
G06F13/36; G06F11/07; G06F13/00; G06F13/38; H04L12/40
Foreign References:
| US20070240019A1 | 2007-10-11 | |||
| US20050262395A1 | 2005-11-24 |
Attorney, Agent or Firm:
Eternal patent business corporation
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