PURPOSE: To obtain a sufficient noise rejection characteristic by using a digital low pass filter so as to eliminate an external noise and inserting a signal compression circuit to the side of a circuit with a clock pass signal given thereto.

CONSTITUTION: A data bus signal is given to an input terminal 1 and a clock bus signal is inputted to an input terminal 2. A clock from a clock input terminal 14 is fed to a clock input of each D.FF of digital low pass filters 12, 13. A signal with an external noise rejected therefrom is reproduced from the filter 13. This is applied also to the filter 12. D.FF 26∼28 and an AND gate 29 are provided to retard to output of the filter 13 by 2 clock periods. The pulse width of the filter 13 is compressed by D.FFs 26, 27 and the AND gate 29 to avoid a problem when the clock frequency of the clock input terminal 14 is lowered. The clock is bypassed through the filters 12, 13, the D.FFs 26∼28 and the AND gate 29 at test by the switches 23, 24.