Title:
BUS MONITORING DEVICE FOR MULTI-CPU SYSTEM
Document Type and Number:
Japanese Patent JPS6488768
Kind Code:
A
Abstract:
PURPOSE:To ensure successive actions for normal CPU boards by adding a system bus monitoring means to a multi-CPU system to produce a resetting signal so that the use of a system bus is inhibited for the CPU board having abnormality in case this defective CPU board is occupying the system bus. CONSTITUTION:A latch port 11 is added to a system bus monitoring device 9 and at the same time, NAND gates 12-15 are added to the input signal lines 2a-5a led from the CPU boards 25 respectively. In case the device 9 has abnormality in one of those CPU boards, e.g., a CPU board 2, '1' is given to the port 11 as an access inhibiting signal to the board 2. Thus the input of an access request signal is avoided to the board 2 and therefore, the access request signals are supplied to other three CPU boards 3-5 only. Thus these three normal CPU boards can perform their actions. In such a way, the availability of a multi-CPU system is improved.
Inventors:
OBA AKIRA
Application Number:
JP24410887A
Publication Date:
April 03, 1989
Filing Date:
September 30, 1987
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
G06F13/00; G06F15/16; G06F15/173; G06F15/177; (IPC1-7): G06F13/00; G06F15/16
Attorney, Agent or Firm:
Yasuo Miyoshi (1 outside)
Previous Patent: 歌唱評価装置およびプログラム
Next Patent: SUPPORTING DEVICE FOR ACQUISITION OF KNOWLEDGE OF PHYSICAL DISTRIBUTION SYSTEM
Next Patent: SUPPORTING DEVICE FOR ACQUISITION OF KNOWLEDGE OF PHYSICAL DISTRIBUTION SYSTEM