PURPOSE: To unnecessitate an exterior circuit and to prevent the delay of a bus cycle by setting a bus width based on bus size information when the central processing unit of information processor performs the access of a page by means of a bus control mechanism.

CONSTITUTION: When a virtual address 101 is supplied from other unit 14 to a memory management unit 11, first, address conversion information is cached in a high-speed conversion buffer mechanism (TLB) 111, and a bus size (BS) bit BS in this page table entry (PTE) information is stored in a register 15 in a bus size designation circuit 13 to be inputted to both input terminal (IOSZEN terminal) T1 and external terminal (IO8/IO16) terminal T2 of a bus control unit 12. At the time of 32 bits, the bus sizing is not performed. At the time of 16 bits, the access to a real memory 2 is performed after the bus sizing to 16 bits. Thus, the exterior circuit is unnecessitated, and the delay of bus cycle is reduced.