To facilitate a data route trial by outputting data for a trial to a system bus, recording the data of the system bus in an order, storing the value of the system bus or stopping it corresponding to a tracing instruction, outputting a trigger instruction, reading stored tracing data and comparing them with the data for the trial.

A CPU 32 controls a trial control part 373, records the data in a register 372 and records a total pattern number driven on the bus 36 in the register 371. The trial control part 373 controls the data input/output of the registers 372 and 371 corresponding to the signals of the CPU 32 and outputs the data for the trial of the register 372 through a bus interface 35 to the bus 36 for the number of the patterns of the register 371. The CPU 32 instructs tracing start to the data of the bus 36 and a control part 33 stores the data of the bus 36 in a memory 34. The CPU 32 stops tracing when storage time elapses, compares the data of the memory 34 with the data for the trial of the register 372 and confirms all malfunctions.