Title:
BUS SUPERVISING CIRCUIT
Document Type and Number:
Japanese Patent JPS6089147
Kind Code:
A
Abstract:
PURPOSE: To attain ease of fault analysis by adding a fault interruption signal from a BUS control circuit to a system master.
CONSTITUTION: A BUS jam supervising timer 14 is provided in a BUS control circuit 10 and when jam occurs in a BUS, the jam supervising timer 14 reaches time-up, a BUS using permission signal BACK is stored in a register 11 and an address signal A is stored in a register 12. Then a fault interruption signal EINT is outputted to a system master module. The system master gives a BUS using request after the input of interruption and after the right of use is acquired, the address signal assigned to the registers 11, 12 is given and collects fault information.
Inventors:
TAKAHASHI YOSHIAKI
INAYAMA TSUTOMU
SEGAWA NOBUYUKI
ISHIDA SABUROU
INAYAMA TSUTOMU
SEGAWA NOBUYUKI
ISHIDA SABUROU
Application Number:
JP19595583A
Publication Date:
May 20, 1985
Filing Date:
October 21, 1983
Export Citation:
Assignee:
HITACHI LTD
HITACHI ENG CO LTD
HITACHI ENG CO LTD
International Classes:
G06F13/00; (IPC1-7): G06F13/00; H04L11/00
Attorney, Agent or Firm:
Katsuo Ogawa
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