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Title:
バスシステムおよびバススレーブならびにバス制御方法
Document Type and Number:
Japanese Patent JP4818820
Kind Code:
B2
Abstract:
A bus system includes one or more bus masters, one or more bus slaves, and a response unit. When an access request to a resource of a bus slave is sent from a bus master, the response unit outputs a wait response that is either a blocking wait response to cause the bus master to perform a blocking wait operation or a non-blocking wait response to cause it to perform a non-blocking wait operation to the bus master if the bus slave is in the wait state.

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Inventors:
Hideki Matsuyama
Application Number:
JP2006158988A
Publication Date:
November 16, 2011
Filing Date:
June 07, 2006
Export Citation:
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Assignee:
Renesas Electronics Corporation
International Classes:
G06F13/36; G06F9/38
Domestic Patent References:
JP4372018A
JP2004110256A
Foreign References:
US6449690
US7155718
US5455924
Attorney, Agent or Firm:
Ken Ieiri



 
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