PURPOSE: To restrict an increase in the number of signal lines for transfer actuation accompanying an increase in the number of processors without providing a signal line for transfer actuation between a bus controller and each processor respectively.
CONSTITUTION: Processors 12 are grouped by a fixed number, and a discrimination number, consisting of fixed high-order bits, for discriminating a group where each processor 12 blongs and an equipment number, consisting of fixed low-order bits by a discrimination signal in the same group, for discriminating each processor 12 among groups are supplied to each processor 12. Then, bus controller 11 and each processor 12 are connected together via bus-actuation request acceptance bus 14, group discrimination bus 15 and data bus 13 and when bus 13 is free, controller 11 sends an actuation request signal to processor 12 via bus 14. In this state, controller 11 gives a permission to send the bus actuation request signal to processor 12, group by group, and sends the group discrimination number from bus 15. Then, processor 12 given the permission sends the actuation request signal to bus 13.
ODAKA NOBUO
KOBAYASHI TSUNEO
| JPS5372541A | 1978-06-28 | |||
| JPS53101245A | 1978-09-04 | |||
| JPS5150619A | 1976-05-04 |