集積されたパワー増幅器を有するCMOSトランシーバ

Japanese Patent JP2004509533

A

The present invention provides a breakdown resistant transistor structure for amplifying communication signals. This structure includes a first NMOS transistor having a source connected to ground and a first gate for receiving the input radio frequency signal. The first gate is disposed above a first insulator and the first NMOS transistor having a first transconductance and a first breakdown voltage associated therewith. Also included is a second NMOS transistor having a source connected to the drain of the first NMOS transistor, a gate connected to the reference DC voltage, and a drain that provides the output for the amplified radio signal, the load being disposed between the reference DC voltage and the drain of the second NMOS transistor. The second gate is disposed above a second insulator, the second NMOS transistor has a second transconductance and a second breakdown voltage associated therewith, and the second insulator may be thicker than the first insulator. This results in the first transconductance being greater than the second transconductance, and the second breakdown voltage being greater than the first breakdown voltage.

Weber, David Jay
Yue, Patrick
Sue, David

JP2002527579A

March 25, 2004

September 14, 2001

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Atheros Communications, Inc.

H01L23/66; H01L27/088; H03F1/22; H03F1/52; H03F3/195; H03F3/24; H03F3/45; H04B1/04; (IPC1-7): H03F1/52; H03F1/22; H03F3/195; H03F3/24; H03F3/45

JPH0644788A	1994-02-18
JPH0738337A	1995-02-07
JPH07211875A	1995-08-11
JPS4840386A	1973-06-13
JPS525254A	1977-01-14
JPH10145148A	1998-05-29

Takehiko Suzue
Satoshi Kono
Makoto Nakamura
Kurata Masatoshi
Takashi Mine
Yoshihiro Fukuhara
Sadao Muramatsu
Ryo Hashimoto

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