Title:
ＣＲ発振回路及び半導体集積装置
Document Type and Number:
Japanese Patent JP5809550
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a CR oscillation circuit that keeps a life intact and is compact and capable of high density packaging, and a semiconductor integrated device.SOLUTION: A signal sent out from the (2n)th inverter in an inverter train comprising m inverters connected in series is supplied to the following first inverter via a capacitor, and a signal sent out from the (2n+1)th inverter is supplied to the first inverter via a resistance. The first inverter supplies a low level signal to the next stage inverter when the level of the signal supplied from a CR circuit comprising the resistance and the capacitor transitions from a state lower than a first logic threshold to a higher state, and supplies a high level signal to the next stage inverter when the level of the signal supplied from the CR circuit exceeds a second logic threshold higher than the first logic threshold and then transitions to a state lower than the second logic threshold.
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Inventors:
Takashi Tomita
Application Number:
JP2011271170A
Publication Date:
November 11, 2015
Filing Date:
December 12, 2011
Export Citation:
Assignee:
LAPIS Semiconductor Co., Ltd.
International Classes:
H03K3/354; H03K3/02
Domestic Patent References:
| JP57087619A | ||||
| JP8154041A | ||||
| JP58017723A | ||||
| JP2008098995A |
Attorney, Agent or Firm:
Motohiko Fujimura
Shigeyuki Nagaoka
Shinji Takano
Shigeyuki Nagaoka
Shinji Takano