Title:
BUFFER MEMORY CIRCUIT
Document Type and Number:
Japanese Patent JP3183956
Kind Code:
B2
Abstract:
PURPOSE: To suppress occurrence of memory slip and to eliminate occurrence of an error in output data by employing two buffer memories connected in series for the buffer memory circuit.
CONSTITUTION: The buffer memory circuit consists of two buffer memories 1,2, write counters 3,5 and read counters 4,6 corresponding respectively to them. The information included in a cell is written in the buffer memory 1 before being written in the buffer memory 2. A dummy cell is inserted by incrementing the write counter by the buffer memory 1 similarly to a conventional method. However, it is not required for the buffer memory 1 to make continuous reading but to read data only when data to be read are left. That is, the condition for memory slip is not tight for the buffer memory 1 and it is not a problem that the write counter for the buffer memory 1 is suddenly incremented and in the case of write to the buffer memory 2, since the sequence is written for each dummy cell, no problem is caused.
Inventors:
Murakami Beni
Jin Uematsu
Hiromi Ueda
Jin Uematsu
Hiromi Ueda
Application Number:
JP19570192A
Publication Date:
July 09, 2001
Filing Date:
July 23, 1992
Export Citation:
Assignee:
NEC
Nippon Telegraph and Telephone Corporation
Nippon Telegraph and Telephone Corporation
International Classes:
H04J3/06; H04L7/00; H04L12/28; H04L13/08; (IPC1-7): H04L12/28; H04L13/08
Domestic Patent References:
| JP683301A |
Other References:
【文献】1990年信学春季大会 B-719
Attorney, Agent or Firm:
Naotaka Ide (1 person outside)