キャッシュの割当方法と装置、記憶媒体、電子装置

Japanese Patent JP7205033

B2

The present disclosure provides a cache allocation method and apparatus, a storage medium, and an electronic device. The method includes: accessing, by a core, a level 3 cache in response to detecting a miss response from each of a level 1 cache and a level 2 cache, wherein the level 1 cache and the level 2 cache are accessed by the core through sending instruction fetching instructions; wherein the instruction fetching instructions are configured to request the level 1 cache and the level 2 cache that are accessed to return an instruction and data, the level 1 cache is a private cache of the core, the level 2 cache is a common cache corresponding to a core set including the core, the level 3 cache is a common cache shared by a plurality of core sets, and the miss response from the level 2 cache carries network slice information; allocating, by a planning unit disposed in the level 3 cache, the plurality of core sets to a plurality of network slices and configuring, by the planning unit, corresponding caches for the plurality of network slices according to the network slice information; and sending, by the planning unit, a hit response to the core, wherein the hit response is configured to return data in a cache of a network slice corresponding to the core set including the core.

cow xinwei

JP2021562299A

January 17, 2023

April 30, 2020

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Thane Chips Technology Company Limited

G06F12/084; G06F12/0806; G06F12/0811

JP2019502996A
JP2015519654A
JP2013502645A
JP2009211649A

US20140189239

Patent Attorney Tsutsui International Patent Office

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