Title:
多重プロセッサアーキテクチャのためのキャッシュコヒーレンシシステムおよび方法
Document Type and Number:
Japanese Patent JP2004505346
Kind Code:
A
Abstract:
A cache coherency directory for a shared memory multiprocessor computer system. A data structure is associated with each cacheable memory location, the data structure comprising locations for storing state values indicating an exclusive state, a shared state, an uncached state, a busy state, a busy uncached state, a locked state, and a pending state. The busy state and pending state cooperate to reserve a cache line for future use by a processor while the cache line is currently being used by one or more other processors.
Inventors:
David Parks
Application Number:
JP2002514544A
Publication Date:
February 19, 2004
Filing Date:
March 16, 2001
Export Citation:
Assignee:
SRC Computers Inc.
International Classes:
G06F9/52; G06F12/08; (IPC1-7): G06F15/177; G06F12/08; G06F15/16
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai