Title:
投機的読取り動作の存在下におけるキャッシュ制御
Document Type and Number:
Japanese Patent JP7389048
Kind Code:
B2
Abstract:
Coherency control circuitry 10 supports processing of a safe-speculative-read transaction received from a requesting master device 4. The safe-speculative-read transaction is of a type requesting that target data is returned to a requesting cache 11 of the requesting master device 4 while prohibiting any change in coherency state associated with the target data in other caches 12 in response to the safe-speculative-read transaction. In response, at least when the target data is cached in a second cache associated with a second master device, at least one of the coherency control circuitry 10 and the second cache 12 is configured to return a safe-speculative-read response while maintaining the target data in the same coherency state within the second cache. This helps to mitigate against speculative side-channel attacks.
Inventors:
Sandberg, Andreas Lars
Deesterholst, Stefan
Nicole lease, Nicos
Caulfield, Ian, Michael
Greenhalgh, Peter Richard
Pirie, Frederic Claude Marie
Tunnel, Alban Pierric
Deesterholst, Stefan
Nicole lease, Nicos
Caulfield, Ian, Michael
Greenhalgh, Peter Richard
Pirie, Frederic Claude Marie
Tunnel, Alban Pierric
Application Number:
JP2020554160A
Publication Date:
November 29, 2023
Filing Date:
March 12, 2019
Export Citation:
Assignee:
Arm limited
International Classes:
G06F12/0815; G06F9/38; G06F9/52; G06F21/55
Domestic Patent References:
| JP2013521556A |
Foreign References:
| WO2000038077A1 | ||||
| US6918009 | ||||
| US20050154836 |
Attorney, Agent or Firm:
Patent Attorney Corporation Asamura Patent Office
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