To provide a cache memory device which operates a cache memory with the lowest possible power consumption while having cache hit performance equivalent to a normal access mode.

The cache memory control circuit includes: a selecting section 42 configured to select each or two or more ways in a cache memory in which several ways have been divided by a predetermined division number, in a predetermined order; a comparison section 33 configured to detect cache hit in each way; a control section 41 configured to, when the cache hit is detected, stop the selection of each way in the selection section 42; and a division number changing section 16b having comparing sections 61 and 62, which compare the two pieces of read data from the cache memory having been propagated through two paths, one of which has a predetermined amount of delay with respect to the other one, and changes the predetermined division number depending on whether the two pieces of the read data coincide with each other in the comparing sections 61 and 62.