Title:
CACHE MEMORY CONTROL SYSTEM
Document Type and Number:
Japanese Patent JP3163132
Kind Code:
B2
Abstract:
PURPOSE: To provide the cache memory control system suitable for accessing continuous data concerning the cache memory control system for controlling a cache memory provided between a storage device and a processor.
CONSTITUTION: Two storing means 11 provided by dividing the entry of a cache memory 4 respectively ho transfer data from a storage device 1, and it is managed which storing means 11 holds new data. This system is provided with a requesting means 8 to request data following to the held data in the storing means 11 to the storage device 1 when holding request data from a processor 2 by any one of the storing means 11, judging means 9 to judge whether the transfer data from the storage device 1 follow to the held data in the storing means 11 or not, and setting means 10 to hold the transfer data in the storing means 11 holding the former data when the judging means judges the transfer of the continuous data.
Inventors:
Tsukasa Aoki
Koichi Yoshimi
Koichi Yoshimi
Application Number:
JP30221291A
Publication Date:
May 08, 2001
Filing Date:
November 19, 1991
Export Citation:
Assignee:
富士通株式会社
株式会社ピーエフユー
株式会社ピーエフユー
International Classes:
G06F12/08; G06F12/12; (IPC1-7): G06F12/08
Domestic Patent References:
| JP1230153A | ||||
| JP503736A | ||||
| JP59225427A | ||||
| JP1223545A | ||||
| JP3116345A | ||||
| JP4365157A |
Attorney, Agent or Firm:
Mitsuyoshi Okada (3 outside)