PURPOSE: To easily perform the test of a tag memory by providing a decoder circuit to generate a way hit signal by receiving a way selection signal, and a third selector to select and output either the way hit signal from the circuit or the way hit signal from a priority storage means.

CONSTITUTION: The decoder circuit 14 which receives the way selection signal from the outside to instruct a specific way and generates the way hit signal, and a selector 15 which receives a diagnostic mode signal 12 and selects and outputs either the way hit signal from the decoder circuit 14 or the one from the priority storage means 8 are provided. And a way is selected with the way selection signal 13 inputted from the outside by setting a mode at a diagnostic mode with the diagnostic mode signal 13. Thereby, algorithm to generate a test pattern for the diagnosis of an address tag memory 5 is simplified.