To provide a cache memory system and a control method for WAY prediction of a cache memory, which reduce failures of WAY prediction by WAY prediction not using address matching and is capable of preventing malfunction of the system.

A cache device 1 includes: a WAY information buffer 79 wherein WAY information being a selection result of WAY in an instruction which has accessed a cache memory 14 is stored; and a control circuit 80 which controls, during repeated execution of a series of instruction groups, storing processing for storing WAY information in the instruction groups into a WAY information buffer 79 and readout processing for reading out WAY information from the WAY information buffer 79.