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Title:
CACHE MEMORY SYSTEM AND CONTROL METHOD FOR WAY PREDICTION OF CACHE MEMORY
Document Type and Number:
Japanese Patent JP2011065503
Kind Code:
A
Abstract:

To provide a cache memory system and a control method for WAY prediction of a cache memory, which reduce failures of WAY prediction by WAY prediction not using address matching and is capable of preventing malfunction of the system.

A cache device 1 includes: a WAY information buffer 79 wherein WAY information being a selection result of WAY in an instruction which has accessed a cache memory 14 is stored; and a control circuit 80 which controls, during repeated execution of a series of instruction groups, storing processing for storing WAY information in the instruction groups into a WAY information buffer 79 and readout processing for reading out WAY information from the WAY information buffer 79.


Inventors:
TAKAHASHI DAISUKE
Application Number:
JP2009216570A
Publication Date:
March 31, 2011
Filing Date:
September 18, 2009
Export Citation:
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Assignee:
RENESAS ELECTRONICS CORP
International Classes:
G06F12/08
Attorney, Agent or Firm:
Ken Ieiri