PURPOSE: To improve the access efficiency to a main memory by making a cache memory grasp the refresh execution timing of the main memory end writing the internal data on the cache memory in the main memory in a refresh state.

CONSTITUTION: A data processor 1 is provided together with a main memory 4 consisting of a storage element (DRAM) which requires the periodical rewrite of data, and a cache memory 2 which holds a part of the storage contents of the memory 4. When the date stored in the memory 2 are rewritten by the processor 1, these rewritten data are written into the memory 4 when the date stored in the memory 4 are rewritten. If the data desired by the processor 1 are not stored in the memory 2, it is desired that plural data including the desired ones are read out to the memory 2 from the memory 4. Then the data of the memory 4 are rewritten in the timing set immediately after the data are read into the memory 2.