PURPOSE: To reduce deterioration in the performance of a processor by providing two address input ports and using an address array cable of making a hit/miss decision on a cache for two logical addresses.

CONSTITUTION: The address array 130 which accepts two access requests at the same time and makes a hit/miss decision on the cache is provided; when the both are hit, hit data are transferred to a processor in preset order and when one is hit, continuation processing of access on the hit side and the swap-in processing on the miss side are carried out in parallel to shorten the stop time of the processor. Even when the both are missed, address conversion and a request to access a main storage are performed in parallel to the swap-in processing of one side, so the stop time of the processor due to a cache miss is shortened.