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Patent Searching and Data


Title:
CALCULATION ASSISTING CIRCUIT
Document Type and Number:
Japanese Patent JP2002159006
Kind Code:
A
Abstract:

To provide a calculation assisting circuit which can be manufactured at a low cost in a short manufacturing time and can be appropriately reduced in circuit scale and improved in computing speed.

An image processing system performs the compression or decompression of image data by the encoding method using the DCT with software and hardware and is constituted by connecting a CPU 40, an external image memory 44, and a calculation assisting circuit 50 to each other through a bus. The calculation assisting circuit 50 is provided with an internal arithmetic circuit 52 and buffers 54-58 which are accessible from both the CPU 40 and circuit 52. Upon receiving an instruction to perform a YUV conversion, an RGB conversion, a quantization calculation, or an inverse quantization calculation, the internal arithmetic circuit 52 reads data from the buffers 54-58, performs calculation including a common calculation which is commonly performed in the above-mentioned calculations based on the plurality of read data, and writes the results of the calculation in the buffers 54-58.


Inventors:
MIYAKOSHI DAISUKE
Application Number:
JP2000349644A
Publication Date:
May 31, 2002
Filing Date:
November 16, 2000
Export Citation:
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Assignee:
SEIKO EPSON CORP
International Classes:
G06F17/14; G06T1/20; H03M7/30; H04N19/42; H04N19/423; H04N19/60; H04N19/625; H04N19/85; H04N19/91; (IPC1-7): H04N7/30; G06F17/14; G06T1/20; H03M7/30
Attorney, Agent or Firm:
Masanori Ueyanagi (1 outside)