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Patent Searching and Data


Title:
CAPACITANCE MULTIPLIER TYPE INTEGRATION DEVICE
Document Type and Number:
Japanese Patent JPS60126773
Kind Code:
A
Abstract:

PURPOSE: To decrease the change of an integration constant due to a current flowing to a capacitor by providing a common base type transistor (TR) to the input of a current amplifier circuit and adding a current feedback circuit to the TR to make the emitter voltage constant.

CONSTITUTION: A capacitance multiplier integration device is provided with a current amplifier TRQ1, one end of a variable current source S2 and of a capacitor C is connected to the collector of the TRQ1 and the emitter is connected to common. Furthermore, a collector of a TRQ2 is connected to a base of the TRQ1 and a base of the TRQ2 is connected to common via a constant current source S1. Moreover, an emitter of the TRQ2 is connected to the other end of the capacitor C by using it as an input and the negative feedback circuit of current mirror connection comprising TRQ3, Q4 is provided between the emitter and base of the TRQ2. Then a current I0+ic flows to the TRQ1 via the TRQ2, the voltage at a point A is made almost constant to decrease the variation of the integration constant and to eliminate the distortion of integration output.


Inventors:
EMORI TAKAHISA
Application Number:
JP23438283A
Publication Date:
July 06, 1985
Filing Date:
December 14, 1983
Export Citation:
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Assignee:
SONY CORP
International Classes:
G06G7/184; (IPC1-7): G06G7/184
Attorney, Agent or Firm:
Akio Waki