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Patent Searching and Data


Title:
CAPACITOR ARRANGEMENT SUPPORT METHOD AND CAPACITOR ARRANGEMENT SUPPORT DEVICE
Document Type and Number:
Japanese Patent JP2013238954
Kind Code:
A
Abstract:

To provide a capacitor arrangement support method capable of more easily setting appropriate arrangement of a capacitor on a multilayer board.

The maximum distance Lmax between a power supply via 121 and a power supply via 141 is computed from width X and length Y of ground wiring 112, width x and length y of power supply wiring 111, width W of power supply wiring, a thickness h of a first dielectric layer, a thickness H of a second dielectric layer, the number n of ground vias 143, 144 connected to a capacitor 220, the number N of power supply vias 141, 142 connected to the capacitor 220, the number m of the ground vias 122 connected to an IC 210, the number M of power supply vias 121 connected to the IC 210, diameters R of the power supply vias 121, 141, 142 and the ground vias 122, 143, 144, impedance Zc of the capacitor 220, a target frequency fT, and target impedance ZT.


Inventors:
TAKATSUJI HIROYUKI
Application Number:
JP2012110375A
Publication Date:
November 28, 2013
Filing Date:
May 14, 2012
Export Citation:
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Assignee:
MURATA MANUFACTURING CO
International Classes:
G06F17/50; H05K3/00; H05K3/46
Domestic Patent References:
JP2001167139A2001-06-22
JPH1115870A1999-01-22
Foreign References:
WO2011151992A12011-12-08
US7047515B12006-05-16
Attorney, Agent or Firm:
Kazuhiro Ueda