Title:
LOGIC VERIFYING DEVICE
Document Type and Number:
Japanese Patent JP3148712
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To make the logic and the connection changeable without changing the print board of an emulator.
SOLUTION: A CPU 122, memory 123, or logic programmable FPGA 121 or the like (logic circuit constituting part or the like) are mounted on a daughter board 112, and an inter-part connection programmable FPID (switch array element) 131 is mounted on a mother board 111. The daughter board 112 is loaded on the mother board 111, and a program is operated to the FPGA 121 and the FPID 131 so that the construction of a logic and the connection of parts can be attained.
Inventors:
Yoshinori Nabeta
Mitsuhiro Kitta
Hiroyuki Yamamoto
Tatsuya Kimishima
Kazuo Chiba
Mitsuhiro Kitta
Hiroyuki Yamamoto
Tatsuya Kimishima
Kazuo Chiba
Application Number:
JP6595698A
Publication Date:
March 26, 2001
Filing Date:
March 16, 1998
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
G06F11/22; G06F17/50; G01R31/28; (IPC1-7): G06F11/22; G01R31/28; G06F17/50
Domestic Patent References:
| JP4198777A | ||||
| JP8221164A | ||||
| JP6110722A | ||||
| JP588801A | ||||
| JP1010196A | ||||
| JP7287720A |
Other References:
”ＡＴＭノードシステムにおけるフレキシブルハードウェア設計法の検討”，電子情報通信学会技術研究報告，１９９７年２月，ＳＳＥ９６−１６５，ｐ．１７−２２
”教育用ＲＩＳＣ型マイクロプロセッサＤＬＸ−ＦＰＧＡとそのラピッドシステムプロトタイピング”，電子情報通信学会技術研究報告，１９９５年４月，ＣＰＳＹ９５−２０，ｐ．７１−７８
”教育用ＲＩＳＣ型マイクロプロセッサＤＬＸ−ＦＰＧＡとそのラピッドシステムプロトタイピング”，電子情報通信学会技術研究報告，１９９５年４月，ＣＰＳＹ９５−２０，ｐ．７１−７８
Attorney, Agent or Firm:
Hiroaki Tazawa (1 person outside)