To provide a latch chain having the improved sensitivity to its input voltage.
The latch chain includes an improved type first latch 14, an amplifier 16, and a conventionally configured type second latch 18 which are connected in series with each other in this order. The first latch 14 is so improved as to have a higher sensitivity and a lower output voltage than the second latch 18. The improved type latch 14 has a pair of output transistors opposed to each other for generating its output voltage and has a pair of first and second bias circuits opposed to each other for applying respectively bias voltages to the bases of the output transistors. During a sampling period, in response to an input voltage inputted to the first latch, a sample stage is so connected with one of the bias circuits, i.e., with the first bias circuit as to apply thereto a first bias current. Further, in response to the input voltage inputted to the first latch during the last sampling period, a hold stage is so connected with the second bias circuit as to apply thereto a second bias current. The sample and hold stages apply respectively different bias potentials from each other to the bases of the output transistors of the first latch. The absolute value of the second bias current is made smaller than the one of the first bias current.
DORSCHKY CLAUS
GEORGE E GEORGIA
GROEPPER CARSTEN
MATTIA JOHN P
PULLELA RAJASEKHAR
REINHOLD MARIO
