Title:
CASH MEMORY CONTROL
Document Type and Number:
Japanese Patent JPS59123952
Kind Code:
A
Abstract:
The method for controlling a single physical cache memory (42) to provide multiple virtual caches in a data processing system including a host processor (10), a data file (16) in which are stored pages of data which may be retrieved by the host processor (10), and I/O controller (20) which controls the transfer of requested data between the host processor (10) and the file (16), consists in dividing the single physical cache memory (42) into a plurality of virtual caches, one of the virtual caches being associated with each of multiple data processing tasks being performed by the host processor (10), and transferring from the file (16) into each of the virtual caches, predetermined amounts of data for at least some requests for data from the file (16) for the associated processing task.
Inventors:
JIERII DEYUAN DEIKUSON
JIERARUDO ARAN MARAZASU
JIERARUDO URURITSUCHI MAAKERU
ANDORIYUU BOISU MAKUNEIRU
JIERARUDO ARAN MARAZASU
JIERARUDO URURITSUCHI MAAKERU
ANDORIYUU BOISU MAKUNEIRU
Application Number:
JP21645283A
Publication Date:
July 17, 1984
Filing Date:
November 18, 1983
Export Citation:
Assignee:
IBM
International Classes:
G06F12/08; G06F12/0842; G06F12/0866; (IPC1-7): G06F13/00; G11C9/06
Domestic Patent References:
| JPS57209555A | 1982-12-22 | |||
| JPS55154648A | 1980-12-02 |
Attorney, Agent or Firm:
Koichi Tonmiya