PURPOSE: To verify a test pattern independently of the description level of a circuit model and to set and verify an arbitrary kind of fault by retrieving a table with an input vector as the key to generate a fault condition list.

CONSTITUTION: The fault propagation technique of the simultaneous fault simulation method is used. In the fault simulation method where an output value and a fault state value are unequivocally determined by an input vector at a point of time, a table of correspondence between inputs and kinds of detectable fault is provided, and the input vector at each simulation time is used as the key to retrieve the table. If fault which can be detected by output pins exists for the input vector, a fault state list is generated for output pins, and the test pattern of a module where the output value and the fault state are unequivocally determined by the input vector is verified independently of the description level of the circuit model, and further, an arbitrary kind of fault is set and verified.