PURPOSE: To eliminate a high frequency component of a shift clock or a reset noise included in an output signal from a CCD linear image sensor and to amplify the signal with one stage of amplifier by adopting a sample-and-hold circuit comprising an analog switch, a capacitor and a differential amplifier.

CONSTITUTION: A black level of an output signal OS1 of a 1st channel of a CCD linear image sensor 10 is sampled and held by an analog switch 13A and a capacitor 17 and a picture level of the signal is sampled and held by an analog switch 14A and a capacitor 18 and the result is sent to a differential amplifier 16A of a fixed gain. A black level of an output signal OS2 of a 2nd channel is sampled and held by an analog switch 13B and the capacitor 17 and a picture level of the signal is sampled and held by an analog switch 14B and the capacitor 18 and the result is sent to a differential amplifier 16B. High frequency component such as reset noise or shift clock of the picture signal thus outputted is eliminated and a balanced signal with excellent quality is obtained.