Title:
CDR CIRCUIT AND MULTI-VALUE MODULATION RECEIVER
Document Type and Number:
Japanese Patent JP2021040268
Kind Code:
A
Abstract:
To suppress the occurrence of a false lock.SOLUTION: A phase detection circuit 13 generates a phase difference signal UP/DN indicating whether to advance or delay the phase of a clock signal CLK when the values of three consecutive symbols is one of data patterns that transition in a slope shape, and a combination of the values of the three symbols and the comparison result in the intermediate symbol of the three symbols matches some predetermined combinations of a plurality of possible combinations of the data pattern and the comparison result in the intermediate symbol, on the basis of a determination result Do output by a data determination circuit 11 and a comparison result output by comparison circuits 12a and 12b.SELECTED DRAWING: Figure 1
Inventors:
KAWAZOE NOBUAKI
YOSHIZAWA KAGEHARU
YAMAZAKI MANABU
YOSHIZAWA KAGEHARU
YAMAZAKI MANABU
Application Number:
JP2019161458A
Publication Date:
March 11, 2021
Filing Date:
September 04, 2019
Export Citation:
Assignee:
FUJITSU LTD
International Classes:
H04L25/02; H04L7/033; H04L25/38; H04L25/49
Attorney, Agent or Firm:
Fuso International Patent Office