To adaptively control a cutoff frequency.

A clock data recovery (CDR) circuit 40 comprises a phase detector 1, a serial/parallel converter 2, a digital filter 3, a phase controller 4, a phase interpolator 5, an integrator 6, a multiplexer 7, and a multiplexer 8. The integrator 6 inputs an output signal SF that is an information signal of a code signal for Early signal [0:n]-Late signal [0:n] calculated by the digital filter 3, monitors the signal for a fixed period M and integrates it as frequency jitter using a delay element and an adder. The CDR circuit 40 changes a threshold of the digital filter and a phase step of the phase interpolator into optimal values and adaptively controls a cutoff frequency.