To provide a CDR circuit that can be generally used, regardless of the presence or absence of a squelch function of an optical receiver at the pre-stage.
A CDR circuit comprises: a G-VCO 14 that outputs a reproduction clock 2 synchronized with input data 1; a flip-flop circuit 12 that identifies and reproduces the input data 1 based on the reproduction clock 2; a sub-VCO 15 that outputs a clock having the same frequency as the clock of the G-VCO 14; a selection circuit 17 that selects one of the reproduction clock 2 and an output clock 4 of the sub-VCO 15; and a frequency comparator 16 that compares the frequency of an output clock 8 of the selection circuit 17 with the frequency of a reference clock 6 and outputs a frequency control signal 5 in response to the frequency difference. The selection circuit 17 selects the output clock 4 of the sub-VCO 15 in a period in which at least the input data 1 is absent and selects the reproduction clock 2 in the remaining period.
KAMITSUNA HIDEKI
OTOMO YUSUKE
山川 政樹
山川 茂樹