To provide a cell sorter and a cell sorting method that can sort cells in a reliable manner without requiring delay time setting for each flow path design.
When a cell C passes between detection electrodes 19a and 19b provided at a previous stage of a sorting circuit, a detection circuit 21 detects the presence of the cell C. If, at this time, a determination signal has been supplied to gate circuits 23 and 24, a flip-flop 25 is set when the presence of the cell C is detected, a switch 27 being ON and a voltage being applied to working electrodes. This changes the course of the cell C. When the cell C passes between detection electrodes 20a and 20b at a subsequent stage, a detection circuit 22 detects the passage of the cell. As a result, a detection signal is supplied to the gate circuit 24, the flip-flop 25 being reset and the switch 27 being OFF. This cancels the formation of working electric fields by a working electrode pair 18.
KATSUMOTO YOICHI
| JP2003287519A | 2003-10-10 | |||
| JP2010181399A | 2010-08-19 | |||
| JP2002543972A | 2002-12-24 | |||
| JP2010025911A | 2010-02-04 | |||
| JP2005319407A | 2005-11-17 | |||
| JP2002233792A | 2002-08-20 |
| US3827555A | 1974-08-06 |
Ori Akira
Teppei Nakamura
Nozomi Yoshida
Ayako Kaneko
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