PURPOSE: To shorten an instruction length in a central processing unit by providing a storage device setting a register executing an operation and an instruction set executing an operation for the register which is set.

CONSTITUTION: The central arithmetic processing device is provided with the storage device setting the register executing the operation shown in a diagram (a), and the instruction set executing the operation for the set register, which is shown in a diagram (b). An OP1 and OP2 setting instruction sets the register which executes the instruction and executes the operation before the instruction shown in the diagram (b) is executed. The arbitrary registers are set for respective OP setting numbers. Since the byte width of the instruction can be reduced, the number of the instructions which are once read into the central arithmetic processing device is increased. Thus, processing speed can be improved. Since the byte width of the instruction is not directly increased by the number of the registers, the number of the registers in the central processing unit can be increased. Since the much more instructions can be executed by the cache memory of a decided size, the hit ratio of the cache memory improves.