Title:
ニューラル推論プロセッサのための中央スケジューラおよび命令ディスパッチャ
Document Type and Number:
Japanese Patent JP7332247
Kind Code:
B2
Abstract:
Neural inference processors are provided. In various embodiments, a processor includes a plurality of cores. Each core includes a neural computation unit, an activation memory, and a local controller. The neural computation unit is adapted to apply a plurality of synaptic weights to a plurality of input activations to produce a plurality of output activations. The activation memory is adapted to store the input activations and the output activations. The local controller is adapted to load the input activations from the activation memory to the neural computation unit and to store the plurality of output activations from the neural computation unit to the activation memory. The processor includes a neural network model memory adapted to store network parameters, including the plurality of synaptic weights. The processor includes a global scheduler operatively coupled to the plurality of cores, adapted to provide the synaptic weights from the neural network model memory to each core.
Inventors:
Cassidy, Andrew, Stefan
Flickner, Myron
Datta, Parab
Penner, Hartmut
Upswami, Lasinakumar
Jun Sawada
Arthur, John, Vernon
Moda, Dalmendra
Esser, Steven, Kyle
Taba, Brian, Saishaw
Clamo, Jennifer
Flickner, Myron
Datta, Parab
Penner, Hartmut
Upswami, Lasinakumar
Jun Sawada
Arthur, John, Vernon
Moda, Dalmendra
Esser, Steven, Kyle
Taba, Brian, Saishaw
Clamo, Jennifer
Application Number:
JP2020556803A
Publication Date:
August 23, 2023
Filing Date:
March 28, 2019
Export Citation:
Assignee:
INTERNATIONAL BUSINESS MACHINES CORPORATION
International Classes:
G06N3/063
Domestic Patent References:
| JP2001188767A | ||||
| JP7219919A |
Foreign References:
| US20140365413 |
Attorney, Agent or Firm:
Tadashi Taneichi