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Title:
CERAMIC BOARD AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3725960
Kind Code:
B2
Abstract:

PROBLEM TO BE SOLVED: To prevent the generation of a discoloration, which is generated in electroless Au-plated layers or an electroless Au-plated layer, when an IC chip is bonded to a ceramic board at about 450°C, in the ceramic board, which has lower electroless Ni- plated layers, upper electroless Ni-plated layers and the electroless Au-plated layers in the order of the low electroless Ni-plated layers, or in the ceramic board, which has an electroless Ni-plated layer and the electroless Au-plated layer on a connection member.
SOLUTION: In the case where this board 10 has metallized layers 2 and 3 formed on the surface of the board 10, lower electroless Ni-plated layers 2a and 3a, which are respectively formed on the layers 2 and 3, upper electroless Ni-plated layers 2b and 3b, which are respectively formed on the layers 2a and 3a, and electroless Au- plated layers 2c and 3c, which are respectively formed on the layers 2b and 3b, in this order of the layers 2 and 3, the layers 2a and 3a, the layers 2b and 3b and the layers 2c and 3c, the layers 2b and 3b are crystallized. Or an electroless Ni-plated layer 5b and an electroless Au-plated layer 5c are provided in this order of the layer 5b and the layer 5c on a connection member 5, formed on the surface of this board 10 and the layer 5b is crystallized. As a method of crystallizing the layers 2b and 3b or the layer 5b, it is preferable to heat the layers 2b and 3b or the layer 5b at 500 to 750°C in a reducing atmosphere.


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Inventors:
Kazuo Kimura
Kazuhisa Sato
Takahiro Shibata
Application Number:
JP9011997A
Publication Date:
December 14, 2005
Filing Date:
March 24, 1997
Export Citation:
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Assignee:
Nippon Special Ceramics Co., Ltd.
International Classes:
H05K1/09; C04B41/52; H05K3/24; (IPC1-7): H05K1/09; H05K3/24
Domestic Patent References:
JP7007243A
JP4261091A
JP2240995A
JP6313434A
JP64045769U